Multiple-input multiple-output (MIMO) solutions typically require synchronization of multiple devices or instruments. Often, MIMO solutions involve complex stimulus response measurements, which require source and receiver synchronization that will not tolerate clock period ambiguity, regardless of the clock frequency. Accordingly, the multiple devices may be synchronized using a reference clock and an open collector signal, which may be referred to as a synchronization signal or “sync.”
For example, devices may use a 10 MHz reference signal to establish a common frequency reference within a measurement system. However, event timing synchronization has typically been achieved through trigger input/output signals, which are treated by each device as asynchronous to the reference signal. Each device generates or interprets the trigger signals based on unique clocks contained within the device. Therefore, timing synchronization has ambiguity based on the independent quantization of time by each device. Additional ambiguity may be incurred at multiple clock boundaries within a single device, further worsening overall trigger jitter.
FIG. 1 is a simplified block diagram showing a conventional MIMO system 100 in which multiple devices 105(1), 105(2), . . . 105(N) in a daisy chain are synchronized based on sync signal 101 and reference signal 102. Each of the devices 105(1) through 105(N) in the chain may be a separate instrument or a separate subsystem, such as a separate plug-in board, within one instrument.
FIG. 1 shows the daisy chain connection using external T's with each device 105(1) through 105(N), where each device 105(1) through 105(N) has a high impedance, low capacitance input. The reference line may be terminated with an external load (e.g., 50 ohms) attached to the final T. Conventional devices typically use 50 ohm terminated reference inputs, so another reference signal 102 distribution uses a matched power splitter driving a star configuration with matched cable lengths. The star connection eliminates the inherent timing skew of the daisy chain. However, it requires a larger drive level of the reference signal 102 at the input of the splitter.
In order to enable synchronization among the devices 105(1) through 105(N), each device may include a sync buffer, which receives the reference signal 102 and the sync signal 101. An example of a sync buffer 200 is shown in FIG. 2. Referring to FIG. 2, the sync buffer 200 receives the reference signal 102 through reference line 112, and the sync signal 101 through sync line 111.
The reference line 112 provides the reference signal 102, which is used as RefIn for synchronizing operations. The reference line 112 may be an unterminated backplane trace (not shown), for example, connected to a single pin on plug-in boards corresponding to one or more devices 105(1) through 105(N). One of the devices 105(1) through 105(N) plugged into the backplane must drive the reference line 102, for example, with transistor-transistor logic (TTL) compatible square wave having a frequency of the reference signal 102. This reference device or reference board, as the case may be, assures that the reference signal 102 on the backplane has a fixed timing relationship to the reference signal 102 on an instrument rear panel. Specifically, if two instruments are locked via the reference signal 102, then the rising edges of their reference signals 102 must be within 10 ns of each other, assuming the reference signal 102 is a 10 MHz signal. It is assumed that the rear panel reference signal 102 input and output are directly cabled to the reference board, not via the backplane. Thus, the 10 ns skew requirement is actually enforced by the reference board design.
The sync line 111 is connected to node 121, which is connected to buffer 122 through resistance 125. The buffer 122 provides a SyncIn signal for marking edges the reference signal 102, as discussed above. More particularly, the device 105(1) will sample a state of the sync line 111 at each rising edge of the reference signal 102. The sync line 111 may also be a backplane trace (not shown), for example, connected to a single pin on plug-in boards corresponding to one or more devices 105(1) through 105(N). A coaxial cable (not shown) is connected from the sync line 111 to an externally accessible rear panel connector.
The sync buffer 200 also includes output buffer 124, which receives SyncOut signal generated by the device 105(1). The output buffer 124 is connected to ground and node 121, which is also connected in series with voltage source V+ through pull-up resistance 135. The value of the pull-up resistance 135 may be chosen to achieve an RC time constant of approximately 25 ns, where C is the total capacitance of the Sync node inside the device 105(1), plus 50 pf for external cable capacitance. This allows 0.5 m of 50 ohm cable per device for sync interconnect. When the device 105(1) has with long internal sync routing, for example, an optional bead (not shown) should be added near the connector of the sync line 111 to provide damping of stub resonance. In the conventional system, the parallel combination of pull-up resistors in the system must be greater than 50 ohms due to the sink current limit of the drivers. This limits the number of instruments which can be connected to the sync line 111.
Also, in this example, the total capacitance of the sync line 111 to ground, with no plug-in boards and no external sync connection, must be less than 67 pf, including the coax to the rear panel connector. The total capacitance of the sync line 111 on the device 105(1), for example, must be less than 11 pf. The dedicated SyncOut and SyncIn signals are connected to the timing control circuit of each participating device, e.g., device 105(1). To minimize capacitance of the sync line 111, the dedicated lines may be routed to a location near the sync connector where all input/output buffering is performed.
The use of sync signal 101 and reference signal 102 in the MIMO system 100, including instruments such as a spectrum analyzer, presents certain problems. A device typically contains multiple sub-systems or boards, each of which is a separate module with regard to the sync signal 101 and the reference signal 102. For example, a swept spectrum analyzer contains a sweeper, which generates a local oscillator (LO) frequency for a first mixer, and a receiver, which captures a final intermediate frequency (IF) signal. During normal operation, these modules of the spectrum analyzer must be synchronized to each other, even if the spectrum analyzer is not synchronized with other instruments. Therefore, a hierarchy of modules arises: A “local” or “instrument” level of the hierarchy includes participating modules within a single instrument and a “global” or “system” level of the hierarchy includes synchronization between instruments.
However, conventional implementations using the sync signal 101 and the reference signal 102 is non-hierarchical, meaning that it does not distinguish between the local and global levels of operation. For example, with respect to automated test equipment (ATE), some measurements require multiple instruments to be synchronized with one another, while other measurements require each instrument to act independently. To accommodate independent operation, the sync line 111 must be physically disconnected to disable the sync connection between the instruments. However, the wired-OR nature of the sync line 111 complicates attempts to automate this disconnection using software control, which hampers ATE applications.
Furthermore, the wired-OR nature of the sync line 111 physically limits the sync line cable. For example, the same transmission line must be used to inter-connect the devices and/or modules within devices, which creates loading problems. Also, transmission line stubs caused by routing the sync line 111 into each instrument cause longer settling time and limit the number of instrument modules which can be connected to a single, non-hierarchical sync line 111.